1. Field of the Invention
The present invention relates to the field of signal processing. More particularly, the present invention relates to the selective correction of Global Positioning System (GPS) carrier phase measurement data to improve output performance when operating in a high signal to noise ratio environment.
2. Art Background
Digital Phase Lock Loops (DPLL) are often used to lock the phase of an internal local signal to an input signal. In a high signal to noise ratio (SNR) environment a high bandwidth DPLL is desirable in order to quickly achieve lock. However, a high bandwidth DPLL does not perform well in a low SNR as the DPLL is not typically sensitive enough. Furthermore, high bandwidth DPLL dictates a higher loop closure sampling rate. This is a significant concern for those devices which implement a DPLL in software. The higher the sampling rate, the greater the system overhead. A low bandwidth DPLL, to the contrary, does not lock as quickly. However, the sampling rate can be lowered and a low bandwidth DPLL provides better sensitivity in low SNR environments.
In most devices utilizing a DPLL, the actual carrier phase measurement value is not important. However, in Global Positioning System (GPS) devices, such as GPS receivers, the actual carrier phase measurement itself is used to perform pseudorange determination which result in receiver location calculations. Further, any dynamic disturbance at the input to the DPLL, as might be occasioned by a sudden movement of the receiver antenna, will translate directly to an error in the pseudorange and thus in the indicated position fix. Restoring the static phase measurement as quickly as possible is important in such applications as surveying with a GPS device. Therefore, the speed at which the loop locks to the input is quite important. In addition, sensitivity at low SNR is also important as prior to achieving lock, the phase measurement value is not considered accurate. If, however, an accurate phase measurement value can be provided prior to achieving lock, then the speed at which the loop locks is not as important and a slower bandwidth DPLL can be used effectively in both low SNR and high SNR environments.